The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for improving cycle time in a Quad Data Rate (QDR) Static Random Access Memory (SRAM) device.
Quad Data Rate (QDR) SRAM devices are currently being manufactured using a high-speed CMOS fabrication process. At the heart of the QDR architecture are two separate Double Data Rate (DDR) ports to allow simultaneous access to the memory storage array. Each port is dedicated, with one performing read operations while the other performs data write operations. By allowing two-way access to the memory array at DDR signaling rates, a quad data rate (QDR) is established.
A QDR SRAM system employs dual circuitry for both the address registers and logic controllers, thus allowing for the dual port architecture. While the WRITE port stores data into the memory storage array, the READ port can simultaneously retrieve data from therefrom. A single reference clock generator controls the speeds of both ports. One signal is passed to both logic controllers, resulting in a smooth flow of data. In addition, the clock generator controls the speed of the read and write data registers, providing consistent core bandwidth and operating rates. If individual timing signals were employed for each circuit, the signals could be slightly mismatched, thus resulting in a stall or crash of the memory system.
In earlier generation double data rate (DDR) devices, the core operations are directly timed from only the rising edge of the reference clock signal. As each address operation is performed, only two data operations can occur. Address operations are performed only during the rising edge of the clock signal. Because only one common data bus (port) is available, simultaneous read and write operations are not available with this technology. Unfortunately, even at higher megahertz clock speeds, DDR SRAM is challenged to provide sufficient bandwidth required by today's high-speed network communications equipment.
In comparison, the differences of QDR signaling versus DDR are evident. In order to facilitate a quad data rate, all data is carried by separate read and write ports. By using a DDR clock with two ports, information can be transferred at four data items per clock (assuming two operations are needed, one read and one write). However, notwithstanding the improved bandwidth provided by QDR SRAM in performing the read operation during the first half of the clock phase and the write operation during the second half of the clock phase, the maximum cycle time of the QDR SRAM is still limited since both the read and the write operations must be performed within one-half clock cycle. In essence, the SRAM performs a complete read and precharge, then a complete write and precharge, all within the same clock cycle.
Accordingly, it would be desirable to implement even further improvements in the cycle time of a QDR SRAM device, such as those used in high bandwidth applications like networking and communications systems.